cache memory

CS Extra 4/5/18: Scrambler - Dynamic Layout Adaptation

Thursday, April 5, 2018
4:15 p.m. in Science 3821
Refreshments at 4:00 p.m. in the Computer Science Commons (Science 3817)

Scrambler: Dynamic Layout Adaptation, presented by Garrett Wang and Pouya Mahdi Gholami, discusses the work they completed with Ana Segebre Salazar and Lex Martin during the summer 2017.

Processors have gotten faster and faster over the last 40 years, but memory speed has not kept up. This creates a bottleneck for programs that access memory, which is all programs. Hardware caches help hide this bottleneck by keeping copies of recently-accessed data close to the processor. Caches often do a good job hiding the memory bottleneck, but when programs use certain combinations of memory locations or access memory in specific patterns, caches can work poorly which makes programs run significantly slower. We have developed a system called Scrambler that detects when the cache is not working well and automatically fixes the program’s memory layout to improve performance.

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